VLSI technology has developed over the years thereby enhancing the performance of chips in terms of three basic constraints viz. delay, power and area. In today’s scenario compact and small digital devices are critical concern in the field of VLSI design, which should perform fast as well as low power consumption. Optimizing the delay, area and power of an adder is a major design issues, as area and speed are usually conflicting constraints. Adders can be designed with conventional CMOS technology but for compact and low power consumption we can design circuit using adiabatic logic and with other technology GDI,ECRL, transmission Gate.