×
Loading...

Cryptographic hardware and embedded systems--CHES 2000 : second international workshop, Worcester, MA, USA, August 17-18, 2000 : proceedings by CHES 2000 (2nd : 2000 Worcester, Mass.)

Book Information

TitleCryptographic hardware and embedded systems--CHES 2000 : second international workshop, Worcester, MA, USA, August 17-18, 2000 : proceedings
CreatorCHES 2000 (2nd : 2000 Worcester, Mass.), Koç, Çetin K., 1957-, Paar, Christof, 1963-
Year2001
PPI300
PublisherNew York : Springer
LanguageEnglish
Mediatypetexts
SubjectEmbedded computer systems, Cryptography, Computer security
ISBN354041455X
Collectionjournals_contributions, journals
Uploadersketch
Identifierspringer_10.1007-3-540-44499-8
Telegram icon Share on Telegram
Download Now

Description

Cryptographic Hardware and Embedded Systems — CHES 2000: Second International Workshop Worcester, MA, USA, August 17–18, 2000 ProceedingsAuthor: Çetin K. Koç, Christof Paar Published by Springer Berlin Heidelberg ISBN: 978-3-540-41455-1 DOI: 10.1007/3-540-44499-8Table of Contents:Software Implementation of Elliptic Curve Cryptography over Binary Fields Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA A High-Performance Reconfigurable Elliptic Curve Processor for GF(2m) Fast Implementation of Elliptic Curve Defined over GF(pm) on CalmRISC with MAC2424 Coprocessor Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies Smartly Analyzing the Simplicity and the Power of Simple Power Analysis on Smartcards Power Analysis Attacks and Algorithmic Approaches to their Countermeasures for Koblitz Curve Cryptosystems A Timing Attack against RSA with the Chinese Remainder Theorem A Comparative Study of Performance of AES Final Candidates Using FPGAs A Dynamic FPGA Implementation of the Serpent Block Cipher A 12 Gbps DES Encryptor/Decryptor Core in an FPGA A 155 Mbps Triple-DES Network Encryptor An Energy Efficient Reconfigurable Public-Key Cryptography Processor Architecture High-Speed RSA Hardware Based on Barret’s Modular Reduction Method Data Integrity in Hardware for Modular Arithmetic A Design for Modular Exponentiation Coprocessor in Mobile Telecommunication Terminals How to Explain Side-Channel Leakage to Your Kids On Boolean and Arithmetic Masking against Differential Power Analysis Using Second-Order Power Analysis to Attack DPA Resistant Software Differential Power Analysis in the Presence of Hardware Countermeasures, Includes bibliographical references and index